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An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation

Publication Date
February 23, 2019
Creator
Item Type
ethesis
Thesis Type
PhD
Supervisors
Keywords

field programmable ga...

Jacobian logarithm

Subjects (LC)

TK Electrical enginee...

Associated Schools / Departments
Department of Electrical and Electronic Engineering
eprints ID
55716
UoN Repository URI
Except where otherwise noted, this item's license is described as
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Name

LLL_Thesis_MINORCORRECTION_NOV18.pdf

Type

Full-text

Description
Examined
Size

5.34 MB

Format

Adobe PDF

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